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asp_sem
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5 years ago

DDR2 SDRAM controller & Avalon Burst

Good day! The question is in the attachment. Thank you in advance.
asp_sem's avatar
asp_sem
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5 years ago

Hello. By shift in this case, I mean that the first value 1 is written at the initial address 25'd800000, and value 2 is read at the same address. And for some reason, the value 1 is read at the final address 25'd1454076.

Signal mem_rd_readdatavalid - this is a signal readdatavalid , and signal mem_rd_readdata - this is a signal readdata of avalon specification (burst transfer).