DDR HPCII calibration successful but then only works briefly

Altera support pointed me at an Altera Wiki entry entitled "Local ready signal issues with Altera external memory controller IP".

This tells me that "A common issue with the local_ready signal is it permanently goes low preventing any further commands from being accepted by the controller, effectively resulting in the controller being "locked up"."

The DRAM controller has a variable "proper_beats_in_fifo", and if I monitor this and ensure it doesn't reach it's max value by holding off writing to the DRAM at regular intervals, then the local_ready signal doesn't go permanantly low and the controller doesn't lock up.