DCFIFO: shoud i set flase path timing

There are two ways forward,

If your clock domains are completely asynchronous then you could use a set_clock_groups command to completely cut timing between the domains. The downside is that it might cut paths that you didnt realise were being made in your design.

Or you can manually false path the clock crossing paths. This is more time consuming but you could avoid other issues by catching all the paths crossing the domain.

Also you can check the SDCs that are used in the design through timequest using report sdc