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Honored Contributor
Honored ContributorDCFIFO: shoud i set flase path timing
HI, Im using a DCFIFO (dual clock fifo) to transfer clock domains. i genreated a DCFIFO, but i get timing violations from 1 clock to the other regards Fifo components. should i "set_f...
Altera_ForumHonored Contributor
Honored Contributorthe false path in the documents refer to something else:
• For paths crossing from the write into the read domain, apply a false path assignment between the delayed_wrptr_g and rs_dgwp registers: set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}] • For paths crossing from the read into the write domain, apply a false path assignment between the rdptr_g and ws_dgrp registers: set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}] im asking if i need to false path between clocks .....
