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I believe there are some recommended timing constraints to use with dcfifo's that might help, see:
page 20 of ug_fifo.pdf "Embedded constraint settings"
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Hi,
thank for the answer.
i already look into that, and the document is unclear.
first it has this:
"When using the Quartus Prime TimeQuest timing analyzer with a design that contains a DCFIFO blockapply the following false paths to avoid timing failures in the synchronization registers"
then after few line we have that:
"The false path assignments are automatically added through the HDL-embedded Synopsis designconstraint (SDC) commands when you compile your design. The related message is shown under theTimeQuest timing analyzer report"
it saying that it adding it using an "HDL-embedded" SDC ...:confused:
any ways, i added those and i still have timing issues.
the question remains:
Do i add a "false path" between those clocks? :confused:
Honored Contributor
