Forum Discussion
AGaru1
Occasional Contributor
5 years ago"DCFIFO first written data: lost!"
Hi all. I'm struggeling with a problem trying to write some datas into a DCFIFO. The write signal (wrreq) is an output from a fsm like this: ...... p_fifo_wr_fsm : process(wrclk, RST) ...
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi,
Could you share the design QAR file, simulation result and testbench for investigation? To generate the QAR file, click on Project > Archive Project.
Thanks
Best regards,
KhaiY