Cyclone V hard memory controller clarification

Hi Dave,

Thanks for commenting. No, I haven't simulated this part of the design yet. I'm sure it is good advice. I spent some time probing the avalon interconnects and DDR controller signals and it got pretty cumbersome in signaltap, so that is probably the way to go if I need to get above 80% efficiency. I've not yet simulated blocks that contain altera IP (though have simulated many blocks that I wrote). That is definitely on my list that I've not gotten to yet.

My post probably should have been titled "is there a way to predict" or "can anyone share their experiences with" the memory controller throughput under simplified conditions.

I can survive for now with the efficiency I'm getting and need to prioritize other tasks. I was hoping to get some feedback on any fundamental barriers I would face when trying to achieve high memory throughput efficiency with fixed write-only transfers from one port.

Thanks again,

Lance