Cyclone V hard memory controller clarification

Hey Lance,

Did you try running a Modelsim simulation? I think you would learn a lot from simulation waveforms, since you can see when a burst on the Avalon-MM interfaces become a burst on the DDR interface. You could then write the testbench to generate sufficient Avalon-MM bursts to saturate the DDR3 interface. In the case of a MPFE, you could create multiple masters and hit the DDR with burst writes only, burst reads only, or combinations of burst write and reads.

Cheers,

Dave