New Contributor
Super ContributorHi,
Thank you for contacting Intel community.
For Cyclone V remote update, have you refer to Remote Update Intel® FPGA IP User Guide below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altremote.pdf
You can also refer to Intel community knowledge base below:
https://community.intel.com/t5/FPGA-Wiki/Remote-update-for-Cyclone-V/ta-p/735947
Let me know your feedback.
Thanks.
Regards,
Aiman
New ContributorHi Aiman,
Thank you for your response and links.
Unfortunately I have no Qsys in my design. Does this core has a detailed documentation?
I already made a design containing a factory image and an application image. Factory image contained the referred altremote core (Remote Update hard IP) and I was able to load the app image by the factory image automatically at startup (by a simple state machine).
Now I am stocked how to write a new application image into my EPCQ32A. I tried to add an ASMI core (altasmi) and load it from an external FIFO source by a small Verilog code but now the altremote core does not work even if I disable the flash writing and I do not understand why. Perhaps the ASMI core switches off the connection of the altremote to the flash but I am not sure and do not know how to test it.
I tried the design referred in ug_altremote.pdf page 40. It seems to be very similar to mine (based on AN603) but the code what I wanted to check is completely missing from the Application image. Is this a valid design?
Istvan
