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BInos's avatar
BInos
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6 years ago

Cyclone IV GX Platformdesigner PCIe Hard-IP Upstream Port Arbitration

Hello! I am using a Cyclone IV GX FPGA with the integrated PCIe Hard-IP. The FPGAs PCIe is connected to an ARMv7 CPU running Linux. In the FPGA Design (with Platfromdesigner) the PCIe Hard-IP's Av...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago
Hie, I am afraid based on your use case, Cyclone IV GX might not have a solution to enable two data-paths with prioritization. tx_ws is basically using the application layer to create a wait state; hence I can't think of a way to meet your use case. Also, this data phase signals are not available in QSYS/Platform Editor environment. Regards, Nathan