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FPGADev's avatar
FPGADev
Icon for New Contributor rankNew Contributor
5 years ago

Cyclone 10 GX PCIe - problems with memory write TLP packages

Hi, we try to port/evaluate a working Cyclone V PCIe application (running with an ARM) to the the DK-DEV-10CX220-A-Kit (running with an X86-64). The OS is on both platforms Linux (5.x.x) with a cus...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Alternatively, you can also generate the example design from the PCIe IP GUI, From the design tap, you can select DMA, and then click on generate example design. But with the Internal descriptor controller enabled, the BAR address has to set to 64 bit- prefetchable memory. Besides that, I don't see there is any other example design available.

Regards -SK