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Waseem1
New Contributor
New ContributorCyclone 10 GX EMIF Package Deskew
I am designing a PCB that has a Cyclone 10 GX FPGA connected to 2 DDR3 chips in fly-by topology. I followed Intel's UG20116 EMIF IP User Guide's layout guidelines in terms of length matching address/...
Hi Waseem1,
Yes, the Quartus will take care of all address/command package delays.
You can see the description in Table 97 from the Cyclone 10 EMIF User Guide.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf#page=106
Regards,
Adzim
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Waseem1,
Yes, the Quartus will take care of all address/command package delays.
You can see the description in Table 97 from the Cyclone 10 EMIF User Guide.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf#page=106
Regards,
Adzim
Waseem1Thank you for the response. Just to be clear, does that include the control signals as well (CKE, ODT, CSn)?
