RicardoC
Occasional Contributor
Occasional ContributorCXL Base Hard IP configuration
Hi, I would like to know how the CXL Base Hard IP can be configured to support CXL.mem protocol, using the CPI to interface with CAFU. Thank you, Ricardo.
Forum Discussion
JonWay_C_Intel
Frequent Contributor
Frequent ContributorHi RicardoC,
In the Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP User Guide (Doc#763328), Section 2.3.4: Base HIP Design Example. The block diagram shows the connections between CPI and CAFU. Is that what you are looking for?
RicardoCOccasional Contributor
Occasional ContributorHi,
I believe you mean R-Tile Intel® FPGA IP for Compute Express Link* (CXL) Design Example User Guide (https://cdrdv2.intel.com/v1/dl/getContent/763513).
That was not actually what I was looking for. Back when I asked the question, I wanted to know if and how the Base HIP could be configured to route CXL.mem requests/responses through the CPI bus, since the Base HIP Design Example strictly exercised CXL.cache traffic. I later realized that some of the changes would be on the Base Class Code, Sub Class Code, Programming Interface, etc.
Are there any other settings that should be modified to support CXL.mem in the Base HIP?
Thank you,
Ricardo.
- JonWay_C_Intel
I have sent you a private message.
