Forum Discussion
JL_P
New Contributor
New ContributorCXL Base Hard IP configuration
The questions are as follows: community.intel.com/t5/FPGA-Intellectual-Property/CXL-Base-Hard-IP-configuration/m-p/1497136#M27707 I also want to know if the CXL Base Hard IP supports CXL.Mem. Thanks
JL_PNew Contributor
New ContributorHi
I know the example design dose not support CXL.Mem, because the code of the example does not have the functionality to handle cxl.mem.
I'd like to know if Base HIP supports the cxl.mem functionality. I've noticed that the CPI interface has corresponding cxl.mem signals. If I parse and process the cxl.mem signals externally, can I then implement the cxl.mem functionality?
