Honored Contributor
Honored Contributorall right manjurgl.
I have generated your Qsys file. can you see attached file one ( image_reset_pin_negative.jpg) the pin's name is "reset_reset_n". this suffix "_n" means negative logic. it is active low. so you have to connect this pin with VCC or reset signal which always high except it is reset. also I have one more advice. the pll has three conduit signals. as Qsys warns you, you should export those signal. especially areset_conduit. you have to export areset_conduit and connect it to GND. when you simulate this module, it will occur problem. did those help you?
