Forum Discussion
lingxi10
New Contributor
New ContributorConfiguring Native PHY IP for QSFP transceiver
Hi there,
We are trying to configure a transceiver on a stratix 10 device. The transmitter and receiver are on same board. The 50Mhz global clock goes through an IOPLL IP core to create 100Mhz clo...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
There are some good recommendations for common transceiver related problems. Please follow this link: https://community.intel.com/t5/FPGA-Wiki/What-steps-can-I-follow-to-ensure-I-don-t-have-transceiver/ta-p/1277330
Regards
