Configuration of FIFO IP depth using constant

Hi,

Can you be more specific? I do not see why it would not be possible.

What IP do you use? Intel's? Custom?

The only problem I can imagine is Platform Designer (Qsys) getting in your way... Are you using it? If not how are you instantiating the IP?

Hi,

Are you using it with IP generator or Platform Designer?

I am generating a FIFO IP using IP catalog window in Quartus. There I can configure the depth and address width of the FIFO.

But what I wanted is to generate a FIFO in such a way that the depth/ address width can be passed to the FIFO IP using a generic parameter while instantiating this FIFO IP component in a wrapper file.

Hi,

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf on how to change the parameter or instantiate using RTL code.