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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

compile error in A10 PCIe hard IP

I am getting this error message when elaborating a PCIe hard IP core with Avalon MM interface (build as a Qsys block with Platform Designer) Error(13224): Verilog HDL or VHDL error at altpcieav_dma_...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Thank you for your reply. I did compile the example design that generates from the GUI, but unable to see the same error. I'm not aware of the error that you reported here. If possible, could you please attach the QAR file that can duplicate the problem, so that I can look into it further? Or you may use the example design as the starting point and see if you can still observe the same problem.

Regards -SK