Forum Discussion
Seadog
Occasional Contributor
Occasional Contributorcompile error in A10 PCIe hard IP
I am getting this error message when elaborating a PCIe hard IP core with Avalon MM interface (build as a Qsys block with Platform Designer) Error(13224): Verilog HDL or VHDL error at altpcieav_dma_...
SeadogOccasional Contributor
Occasional ContributorThis post is not about a simulation problem - this is about a compile error when elaborating the design in Quartus.
