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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

compile error in A10 PCIe hard IP

I am getting this error message when elaborating a PCIe hard IP core with Avalon MM interface (build as a Qsys block with Platform Designer) Error(13224): Verilog HDL or VHDL error at altpcieav_dma_...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Daniel,

In order to better assist you, it will be great that if you can share the PCIe AVMM IP setting, and also what simulator that you are using?

From my side, I have performed the following test but did not see the problem in simulation:

  1. Generate the PCIe Gen3x4 AVMM example design from Platform designer by using Quartus v18.1
  2. Open Modelsim SE-64 10.6d
  3. Change the directory to /pcie_example_design_tb/pcie_example_design_tb/sim/mentor
  4. Type ld_debug from the transcript
  5. Add waveform
  6. Type run -all from the transcript
  7. The simulation is a success : - SUCCESS: Simulation stopped due to successful completion!

Regards -SK