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SBure's avatar
SBure
Icon for New Contributor rankNew Contributor
7 years ago

Clocked Video Input II valid resolution bit never rises

My test chain is TPG II() -> CVO II -> wire loop outside qsys -> CVI II. Video resolution is 1080, interlaced, embedded sync. I apply preset SDI 1080i in CVO and CVI parameter editor, only change it ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Sergey,

Do you get expected output from VCO ?

Do you face this issue at hardware or sim ? It will be easier to debug in sim if possible ?

Which Quartus version that you use ?

I can try look for working CVO to CVI sim design so that it's easily to compare and debug your issue.

Thanks.

Regards,

dlim