Altera_ForumHonored Contributor13 years agoClock input port inclk[0] of PLL Error Hi, I have the following Problem: Error (15065): Clock input port inclk[0] of PLL "DE0_Nano_uCE0_Nano_uC_inst|clocks_0:the_clocks_0|altpll: DE_Clock_Generator_Audio|altpll_o152:auto_generated|...Show More
Recent DiscussionsCyclone-V SCFIFO with M10K/MLAB memory - adding ECCAgilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wantedAgilex 7 slew rate reconfigurationSolvedAgilex-7 AXI MCDMA for PCIe hangConstraints not being picked for DCFIFO