clock frequency limit for ddr3 using EMIF ip on arria V fpga

Hi Sir,

Thank you for the information. Just an extra sharing on below.

Please noted on the Core-to-Periphery (C2P) timing miscorrelation affecting Arria V and Arria V SoC. The timing model update is not included in Quartus version 14.1, you have to apply workaround as mentioned in below KDB:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06222015_999.html

I acknowledge that the timing is clean at your side, but just to be safe, i suggest you to consider using Quartus version 15.0 Update 2 as the timing model is included automatically and user doesn't need to use the workaround.

Thanks

Regards,

Aida