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VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

clock frequency limit for ddr3 using EMIF ip on arria V fpga

Hi, I am using ddr3 in my project, i need high throughput as much high as possible. My ddr3 part number is in the following link https://www.components-store.com/product/Micron-Technology/MT41J128M1...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

Thank you for the information. Just an extra sharing on below.

Please noted on the Core-to-Periphery (C2P) timing miscorrelation affecting Arria V and Arria V SoC. The timing model update is not included in Quartus version 14.1, you have to apply workaround as mentioned in below KDB:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06222015_999.html

I acknowledge that the timing is clean at your side, but just to be safe, i suggest you to consider using Quartus version 15.0 Update 2 as the timing model is included automatically and user doesn't need to use the workaround.

Thanks

Regards,

Aida

  • VenkateshSathar's avatar
    VenkateshSathar
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    Thanks for the suggestion. I applied the patch required for the tool and seen the timing. The Timing is fine. I mean for a working 450MHz and not working 533MHz I see the timing same. So, regarding the other suggestions you mentioned above I am trying still. I will come back to you as soon as I get some result.

    Any other suggestions you have.. I request you also to check EMIF Spec estimator mentioned above for the fpga part number I gave.