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NWein's avatar
NWein
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cannot get Cyclone 10 GX HDMI RX to lock

I'm using the Intel HDMI 2.0 RX IP on a Cyclone 10 GX, Quartus Prime Pro 20.2. I cannot get it to lock at any frequency. My video source is a Teledyne-Lecroy HDMI analyzer, so I feel comfortable th...
  • Deshi_Intel's avatar
    Deshi_Intel
    5 years ago

    Hi Neil,


    We suspect HDMI Rx failure encountered at your site is expected because you removed NIOS II design block which also function to perform CDR refclk switching from CDR refclk0 to CDR refclk1.

    • Your modified HDMI Rx design is now stuck with wrong (CDR refclk0) instead of using correct TMDS clock (CDR refclk1).


    In short, I believe you can follow below guideline that I drafted


    Guideline for modification to HDMI Rx only design should be like below :

    1. Option A : for customer that required quick XCVR power up calibration
    • Remove everything else but keep (HDMI Rx top, NIOS II design and also the design code with comment "// Workaround for long power-up calibration issue")
    1. Option B : for customer that doesn’t need “quick XCVR power up calibration” requirement
    • Remove everything else including NIOS II design, just keep HDMI Rx top only
      • Modify gxb_rx NativePHY IP to change default CDR refclk to 1 (refer to attached pic)
      • regenerate gxb_rx IP and recompile HDMI design again

    I am sorry Malaysia Cocid-19 situation is pretty bad where we are not allow to go back office until early Dec. I need to rely on you for now to help verify the HDMI design on hardware.


    Thanks for your understanding.


    Regards,

    dlim


Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Neil,


The forum private message attachment feature is broken but this forum post attachment feature is working. So, I have attached the pic explaining the fitter error to you.


In short,

  • your hdmi_rx_devboard_restored project assigned transceiver rx_cdr_refclk0 pin to a IO_clk (pin_F23) which caused Quartus fitter error
  • while your hdmi_rx_prototype_restored project assigned rx_cdr_refclk0 pin to a transceiver dedicated refclk (pin_R24) which is good and correct


Just wonder do you aware you can actually generated HDMI example design that target C10 GX dev kit board directly from HDMI IP ?

  • I can see that HDMI example design assigned rx_cdr_refclk0 (usb_refclk_p) to transceiver dedicated refclk (pin_U24)
  • You can follow similar pin setting


Thanks.


Regards,

dlim


  • NWein's avatar
    NWein
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    I did not use R24 on the devboard because it is routed to the PCIe connector, and that will not be connected to anything. U24 should be OK, I will give that a try.

    I am aware that it's possible in theory to target the design to the devboard, but for whatever reason that is not working correctly on my Quartus install right now. When I go to select a board to target, the pull-down shows no options at all. Therefore, I had to manually assign everything.

    I will report back with the results of my compilation and test with the new clock pin assignment.