Forum Discussion
Occasional ContributorCannot get Cyclone 10 GX HDMI RX to lock
Hi Neil,
We suspect HDMI Rx failure encountered at your site is expected because you removed NIOS II design block which also function to perform CDR refclk switching from CDR refclk0 to CDR refclk1.
- Your modified HDMI Rx design is now stuck with wrong (CDR refclk0) instead of using correct TMDS clock (CDR refclk1).
In short, I believe you can follow below guideline that I drafted
Guideline for modification to HDMI Rx only design should be like below :
- Option A : for customer that required quick XCVR power up calibration
- Remove everything else but keep (HDMI Rx top, NIOS II design and also the design code with comment "// Workaround for long power-up calibration issue")
- Option B : for customer that doesn’t need “quick XCVR power up calibration” requirement
- Remove everything else including NIOS II design, just keep HDMI Rx top only
- Modify gxb_rx NativePHY IP to change default CDR refclk to 1 (refer to attached pic)
- regenerate gxb_rx IP and recompile HDMI design again
I am sorry Malaysia Cocid-19 situation is pretty bad where we are not allow to go back office until early Dec. I need to rely on you for now to help verify the HDMI design on hardware.
Thanks for your understanding.
Regards,
dlim
Regular ContributorHI,
Based on your update, looks like you will be getting Intel C10 GX dev kit to validate the HDMI example design ?
Yup, this is good move. Pls bring up HDMI example design on Intel C10 GX dev kit board to validate your hardware setup first before switching to your own design.
Below is the HDMI design user guide doc for your reference
Thanks.
Regards,
dlim
Occasional ContributorRegrettably, I am having trouble compiling my design for the dev board. I'm seeing an error I've seen before; last time I went through a very long and involved tech support case and although it was eventually fixed we never really got a clear explanation of the problem, so now I once again have no clue how to address it.
I am seeing this error, for each of the three transceiver channels:
Error(11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" cannot connect to PLD port "O[0]" of "IO_INPUT_BUFFER" for node "c10_refclk2_p~input".
I have tried using other clock inputs instead of refclk2 and there's no change. Until I can get past this I can't do anything.
Here's all the extra info that comes with the error:
Extra Info(13133): Output port's "O[0]" node name is "c10_refclk2_p~input".
Extra Info(13134): Input port's "REF_IQCLK[0]" node name is "ehive_hdmi_only|hdmi0|hdmi_rx_top|u_gxb_rx|gxb_rx|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux".
Extra Info(12877): Output port "O[0]" of "IO_INPUT_BUFFER" can connect to:
Extra Info(12878): Port "INCLK[0]" of "CLKBUFBLOCK".
Extra Info(12878): Port "INCLK[0]" of "CLKSELBLOCK".
Extra Info(12878): Port "INCLK[1]" of "CLKSELBLOCK".
Extra Info(12878): Port "INCLK[2]" of "CLKSELBLOCK".
Extra Info(12878): Port "INCLK[3]" of "CLKSELBLOCK".
Extra Info(12878): Port "DATAIN[0]" of "DELAY_CHAIN".
Extra Info(12878): Port "I_INCLK[0]" of "CLKBURSTBLOCK".
Extra Info(12878): Port "I_RXN[0]" of "HSSI_PMA_RX_BUF".
Extra Info(12878): Port "I_RXP[0]" of "HSSI_PMA_RX_BUF".
Extra Info(12878): Port "I_RX_N_BIDIR_IN[0]" of "HSSI_PMA_TX_BUF".
Extra Info(12878): Port "I_RX_P_BIDIR_IN[0]" of "HSSI_PMA_TX_BUF".
Extra Info(12878): Port "I_REFCLK_INN[0]" of "HSSI_REFCLK_DIVIDER".
Extra Info(12878): Port "I_REFCLK_INP[0]" of "HSSI_REFCLK_DIVIDER".
Extra Info(12878): Port "I_RXP[0]" of "HSSI_PMA_CDR_PLL".
Extra Info(12878): Port "I_PIN_PERST_N[0]" of "HSSI_GEN3_X8_PCIE_HIP".
Extra Info(12879): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" can connect to:
Extra Info(12880): Port "O_REFCLK_A[0]" of "HSSI_REFCLK_DIVIDER".
