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RDC's avatar
RDC
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5 years ago

Cannot compile FIR II IP in Quartus 19.3

Hi, I generated a decimator using FIR II IP in Quartus Prime Pro 19.3. Simulation is OK using Modelsim. However when I include the FIR II IP in my project and click "Start Analysis & Elaborat...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Just to follow up with you on this. Thank you.


RDC's avatar
RDC
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5 years ago

Hi, thanks for the following up. The problem remain unsolved.

Sorry that I should have described my problem more clearly.

My situation is that my original project has two FIR IPs, one for Low pass filter and one for decimator.

This project can be synthesized, fit, place & route successfully.

And the function works fine.

When I want to add one more decimator to this project, or more FIRs into this project.

Some error occurs during Analysis and Elaboration.

Like:

Instance "dl_data_top|dl_data_path_ant1|dl_rf_intf|fir_ul_q|fir_compiler_ii_0|fir_deci_2_altera_fir_compiler_ii_191_t3vwpwy_ast_inst|real_passthrough.hpfircore_core" instantiates undefined entity "fir_deci_2_altera_fir_compiler_ii_191_t3vwpwy_rtl_core"

If I click the Hierarchy, then it did show Can't find design entity "real_passthrough.hpfircore_core"

But when I click the File, the file "fir_deci_2_altera_fir_compiler_ii_191_t3vwpwy_rtl_core.vhd" does exist

Not sure if this issue related to

Why Analysis and Synthesis fails when using multiple variation of same DSP IP core

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb331705.html

or

Quartus Compilation Fails in Quartus Prime Pro For Designs with Multiple SerialLite III IP Core Instances

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10082012_901.html

The error message is similar to the multiple SerialLite III IP Core.

Thanks for answering.

  • RDC's avatar
    RDC
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Just offering some additional snapshot for comparison.

    Here is the FIR IP in the original project which can be synthesised, where the "real_passthrough.hpfircore_core" in this FIR IP is defined.



    When I add new FIR IP, error message occurs as the previous post.

    And the "real_passthrough.hpfircore_core" in the new FIR IP is undefined.


    Not sure if I need additional setting for IPs.

    Thanks.

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi,

      Thanks for your update. For your information, I have created simple test design with 3 FIR decimators. 2 are instantiated from the same HDL files. 1 is with different HDL files. Seems like there is no issue running the compilation till Fitter. I am using Q19.4Pro and S10 devices as these are currently available in my local PC.

      You may refer to see if can spot any anomaly with yours. Thank you.