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LHøi0's avatar
LHøi0
Icon for New Contributor rankNew Contributor
6 years ago

Can the altera_pll version 18.0 be used on Cyclone V without the RREF_TL pin connected?

We are using a 5CEBA2F17C8N, 60 MHz input clock, PLL output clock also 60 MHz, feedback mode is "normal". After an IP upgrade the PLL stopped running. The upgraded PLL IP version was 18.1. Copying al...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ,

Kindly find the explanation for the above.

What exactly is the function of RREF_TL pin?

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

Reference :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

Use the above recommendation >> to connect 2Kohm resistor necessary for stable operation of PLL ? We are not using any transceiver channels.