Forum Discussion
New ContributorCan nPERST pins be used as PCIe reset if Intel® Stratix® 10 PCI Express* Hard IP is used as Root Complex?
Hi ,
I will share you one design , I hope it is publicly available with Root port .
Use the below as reference
Kindly have reference.
https://rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI
Frequent ContributorHi ,
The pin_perst configured as input ?
>> Yes
From the screen shot, pin_perst is just an internal signal
>> Yes you are right, it is an internal signal . This internal signal pin_perst of each hard IP instance to the corresponding nPERST pin of the device. ( Reference pag no: 48) , also attaching the screen shot also for easy reference.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf
Do you mean when S10 is setting as root port, nPERST pin can be used and be configured as output?
>> No
New ContributorSo how to control the PCIe reset? In this case, both Root port and End port are input signals. Connect a FPGA I/O pin with S10 nPERST and End Port PCIe reset?
