Forum Discussion
Wujun
New Contributor
New ContributorCan nPERST pins be used as PCIe reset if Intel® Stratix® 10 PCI Express* Hard IP is used as Root Complex?
Hello, According to the Pin Connection Guildline, Pin Functions of nPERST[L,R][0:2] are input or I/O. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin. ...
Hi ,
I will share you one design , I hope it is publicly available with Root port .
Use the below as reference
Kindly have reference.
https://rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi,
Is it mean when I use this pin as fundamental reset, this pin is input?
>> Input
If I use the PCIe hard IP as PCIe Root Complex, do I need to assign a GPIO as fundamental reset? >> NO
Kindly find the explanation
When the PCIe HIP on a side (left or right) is enabled, the nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe nPERST signal to ensure that both ends of the link start link-training at the same time.
