Altera_ForumHonored Contributor10 years agoBug in V Series Avalon MM for PCI Express When using this component with QSYS (even with a simple example) a compilation error is obtained, because tlbfm_out is declared as OUTPUT in the VHLD/Verilog that references the component pcie_256_av...Show More
Altera_ForumHonored Contributor10 years agoBy the way, you might also want to report this to Altera to get them fix the bug.
Recent DiscussionsTeransceiver & FPGAWhy does Fitter show "Dedicated Pin" as "Reference Clock Source by" for downstream PLL in cascade?SolvedAgilex‑7 F‑Tile Dynamic Reconfiguration Conflict Between HDMI and SDI RXJESD204B Multi-Link Implementation with AD9695 ADCs Having Different Lane Counts (L=4 and L=2)Cascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packets