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AFies
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4 years ago

Bug in latest Avalon Streaming Dual Clock FIFO

Hello, I probably discovered a bug in the st_dc_fifo, latest Version 19.4.0, packet mode. sim sources are generated for VHDL by qsys-generate. As you can see on the screenshot of modelsim, the i...
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AFies
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3 years ago

I see, another attempt: I included the exact data listing and waveform file for this simulation in the attached zip. Please check if you can view it. The bug occurs almost at the end of the trace.