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AFies's avatar
AFies
Icon for New Contributor rankNew Contributor
4 years ago

Bug in latest Avalon Streaming Dual Clock FIFO

Hello, I probably discovered a bug in the st_dc_fifo, latest Version 19.4.0, packet mode. sim sources are generated for VHDL by qsys-generate. As you can see on the screenshot of modelsim, the i...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,

I tried opening the .ip file that you had attached in the zip file, but not able to open in Quartus for some reason. However, I too had instantiated the IP and ran the simulation, but did not find any issue.

Attaching the .qar file and the waveform file.

Regards,