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AFies
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4 years ago

Bug in latest Avalon Streaming Dual Clock FIFO

Hello, I probably discovered a bug in the st_dc_fifo, latest Version 19.4.0, packet mode. sim sources are generated for VHDL by qsys-generate. As you can see on the screenshot of modelsim, the i...
AFies's avatar
AFies
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3 years ago

I attached the ip core configuration that was used and still results in this bug.

fwiw, I workarounded it by using a plain DC fifo and emulating valid/ready with full/wrreq/rdreq etc. for now. This works without any other changes, which is another indication that we do have a bug here.

Unfortunately I naturally do not a have a seperate test case for the IP core, the bug happens embedded in a larger unit test which requires our local framework to execute. If there are methods how I can extract the relevant part as a stand-alone test for your analysis, please let me know (ModelSim DE 2021.2 rev 2021.04 linux).