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AFies's avatar
AFies
Icon for New Contributor rankNew Contributor
4 years ago

Bug in latest Avalon Streaming Dual Clock FIFO

Hello, I probably discovered a bug in the st_dc_fifo, latest Version 19.4.0, packet mode. sim sources are generated for VHDL by qsys-generate. As you can see on the screenshot of modelsim, the i...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Sorry for the inconvenience. Can you please provide steps or files to reproduce the issue?


Regards