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AFies's avatar
AFies
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4 years ago

Bug in latest Avalon Streaming Dual Clock FIFO

Hello, I probably discovered a bug in the st_dc_fifo, latest Version 19.4.0, packet mode. sim sources are generated for VHDL by qsys-generate. As you can see on the screenshot of modelsim, the i...
AFies's avatar
AFies
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4 years ago

This sounds like waiting until customers eventually stop complaining is the standard procedure?

The bug was reported almost a year ago and nothing has changed. It still needs to be addressed and I am definitely not impressed by the way Intel handles such issues.