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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Bad timings for MSGDMA IP on Agilex 7 FPGA

Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Thank you for the acknowledgment. Since there are no further questions regarding this case, I will transition this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day!


Best Regards,

Richard Tan