Forum Discussion
Mikhail_a
Occasional Contributor
Occasional ContributorBad timings for MSGDMA IP on Agilex 7 FPGA
Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
Mikhail_aOccasional Contributor
Occasional ContributorAnyways thank you for your help. At least I was able to get rid of some timing issues.
