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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Bad timings for MSGDMA IP on Agilex 7 FPGA

Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

I apologize for any inconvenience caused by the design functionality not meeting your requirements.


Indeed, you are correct. Without changing the IP configuration setting to Aligned Mode, achieving timing closure with a 512-bit data width becomes very challenging, even with the design pipelined.

Just fyi, though it may not be your desired functionality, it is still possible to meet timing requirements with a smaller 32-bit data width in unaligned mode.


Best Regards,

Richard Tan