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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Bad timings for MSGDMA IP on Agilex 7 FPGA

Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side?


Best Regards,

Richard Tan


Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello Richard.

Your recommendation did help me to improve timing issues, not WNS is only -0.2, but unfortunately it affected the functionality of my device and with these settings it stopped working. As I understood there are no ways to improve timings without changing DMA IP settings? If yes then I thing this topic can be closed.