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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Bad timings for MSGDMA IP on Agilex 7 FPGA

Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

The timing can be met by changing the msgdma configuration setting, with the "Aligned Accesses" option checked for the TX mSGDMA, and "Aligned Accesses" option + "No Byteenables During Writes" option selected for RX mSGDMA.

The data width of the DMA is set to a very wide 512-bit, making it difficult to meet timing requirements.

1) In unaligned mode, the input mux will be synthesized for the data path to perform a barrel shift and align the data correctly. This will result in a logic depth of a few layers and a width of 516 bits. Leading to increased logic utilization within the DMA and in the Qsys fabric.

2) In aligned mode, this requires the byte enable generator logic to post Avalon supported byte enables to the fabric. It support hardcoded high byte enables which should make this logic go away.

Best Regards,

Richard Tan