Forum Discussion
Mikhail_a
Occasional Contributor
Occasional ContributorBad timings for MSGDMA IP on Agilex 7 FPGA
Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera
Super Contributor
Super ContributorAre you able to create a simplified design with the replicated issue?
Best Regards,
Richard Tan
Mikhail_aOccasional Contributor
Occasional ContributorHello Richard!
Yes I've created a new design from scratch and got the same issue with timings. Here is a project archive in attachments.
