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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Bad timings for MSGDMA IP on Agilex 7 FPGA

Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Understood that you are unable to provide the full .qar design. In that case, would it be possible for you to create a simplified version of the design that replicates the issue? As I am not expert in PCIE IP, so it may takes times to duplicate the issue.

This will allow us to focus specifically on the problem area.

Thank you for your understanding.


Best Regards,

Richard Tan


  • Mikhail_a's avatar
    Mikhail_a
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thank you for your answer.

    I will provide you with such design as soon as possible.