Forum Discussion

Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Bad timings for MSGDMA IP on Agilex 7 FPGA

Hello! I have a design based on AGFB014R24B2E2V FPGA device. This design implements a simple general NIC functionality and PCIe for connection to the host. Design is clocked by PCIe user clock and ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

In the timing analyzer report, do you see any issue in the Fmax Summary report?

Also, the configuration of the IP may impact the timing closure of this IP.

Could you please provide me with your .qar project file so that I can investigate the issue further?

This will help me analyze the design and provide you with more accurate insights.

Thank you in advance.

Best Regards,

Richard Tan

  • Mikhail_a's avatar
    Mikhail_a
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello Richard.

    Thank you for your answer.

    Unfortunately I can not provide you .qar file, but the design is pretty simple as there are 2 MSGDMA (stream to MM and MM to stream) directly connected from one side to MCDMA (PCIe) IP configured as BAM+BAS and from the other side to Avalon Stream Pipeline stage IP.

    Fmax report shows something like 170MHz max frequency.

    MSGDMA config is shown below. It is the same for both IPs (except of course the DMA mode).

    Prefetcher is disabled.