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Altera_Forum
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10 years ago

avalon wrapper for FIR filter only in VHDL

Hi, I want to use a third party verification tool (ModelSim), that supports only Verilog (and SV). Trouble is, my design includes several FIR filters, which have a "A VHDL wrapper file for the A...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Modelsim supports mixed language if you have an expensive enough licence.

Otherwise, you need to re-write the VHDL to Verilog.

Otherwise write your own, Parameterisable avalon ST wrapper. Its not a very complicated interface (with a ReadyLatency setting of 0 - it can connect directly to a lookahead FIFO).