Avalon-MM slave burst problem?

Hi Dave -

Yes, an SR is the next step (always reluctantly - I've had very mixed results with SRs over the years). When I started this effort I let Qsys generate the testbench and instantiate all of the BFMs, but I got errors when vsim loaded and ran the testbench. I filed a SR for that one. Ends up the problem was that Qsys generates a verilog testbench but the BFMs use system verilog features, so it's broken right out of the box. I should have caught that myself but the ModelSim error message was pretty cryptic and I have never used system verilog. Easy fix by changing the file extension from .v to .sv and editing the msim_setup.tcl script to compile the testbench as a system verilog file. But by the time I got that response to the SR (several days later, which is one of the problems with SRs) I had already moved on to your method of including the BFMs in the Qsys system and then writing your own sv testbench. Your tutorial saved me a ton of time figuring out how to set up the testbench and use the BFMs. Thanks again!

Bob