Forum Discussion
Avalon MM Slave - What's the simple way to extract the above lines from QSYS to HDL?
- 4 years ago
Hi,
The proper way in my opinion would be to instantiate a "Avalon-MM Pipeline Bridge" IP in your Qsys.
You connect its slave interface to the Nios master and export IP's master side.
When you instantiate the qsys in your hdl, the Avalon signals will be there for you to connect to your component.
As for your other question, what are you trying to do? I would say you can simply export anything from your Qsys to wherever it is instantiated.
Hi,
The proper way in my opinion would be to instantiate a "Avalon-MM Pipeline Bridge" IP in your Qsys.
You connect its slave interface to the Nios master and export IP's master side.
When you instantiate the qsys in your hdl, the Avalon signals will be there for you to connect to your component.
As for your other question, what are you trying to do? I would say you can simply export anything from your Qsys to wherever it is instantiated.
- Amir34 years ago
Occasional Contributor
I'm just trying to properly connect the Avalon MM BUS to the comp I make in VHDL code.
Following the solution you proposed with the "Avalon-MM Pipeline Bridge", I read on the Internet that it is possible to produce a component in QSYS that simply connects the BUS to HDL directly. On the one side it connects to the BUS as a Slave and on the other side it connects the same signals of the Avalon MM Slave and allows the above signals to be output to HDL. Do you recommend this implementation?
- sstrell4 years ago
Super Contributor
I think you are referring to simply exporting an interface. Any interface in Platform Designer can be exported so it can be connected to the rest of your Quartus project (when instantiating the Platform Designer system elsewhere in your project hierarchy) or directly to I/O pins (if your system is to be the top level of your Quartus project). You can see from the instantiation template, available in the Generate menu in Platform Designer, what signals would be in your port mapping when you export an interface and then instantiate the system.