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JPovo's avatar
JPovo
Icon for New Contributor rankNew Contributor
7 years ago

Avalon MM Master and Slave need to have the exact same signals?

Hello, I am using the "mem_if_ddr3_emif_0 - DDR3 SDRAM Controller with UniPHY Intel FPGA IP" to acces the DDR3 external memory. In Platform Designer (QSys), Quartus 18.1. I have my own readmaster c...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

It's very likely that one of those other interfaces is holding onto the DDR interface (not clear from your response if any other master is connected to this memory), preventing your master from having access. Can you temporarily disable other components or increase the arbitration priority for this master's access to the memory?