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JPovo
New Contributor
New ContributorAvalon MM Master and Slave need to have the exact same signals?
Hello, I am using the "mem_if_ddr3_emif_0 - DDR3 SDRAM Controller with UniPHY Intel FPGA IP" to acces the DDR3 external memory. In Platform Designer (QSys), Quartus 18.1. I have my own readmaster c...
JPovoNew Contributor
New ContributorSlave is just that one DDR3 SDRAM Controller and there are 6 avalon channels. 3 masters to write data, 1 read/write for pci_debug from ARM MCU and 1 for DMA also for the ARM MCU.
