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JPovo's avatar
JPovo
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7 years ago

Avalon MM Master and Slave need to have the exact same signals?

Hello, I am using the "mem_if_ddr3_emif_0 - DDR3 SDRAM Controller with UniPHY Intel FPGA IP" to acces the DDR3 external memory. In Platform Designer (QSys), Quartus 18.1. I have my own readmaster c...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

You don't need to add them to your master if you don't want/need to do burst accesses. However, the interconnect will get generated automatically with logic to handle this burst signaling.

  • JPovo's avatar
    JPovo
    Icon for New Contributor rankNew Contributor
    7 years ago

    Well, I thought just so, but when I connect just: read, readData, waitRequest and address, the waitRequest goes up with read and never ends. However, if I hold read just for one cycle ignoring the waitRequest, the waitRequest then goes down together with read and the data appears a few cycles after - just like pipeline reading... (and my master didnt have readDataValid signal here)