Forum Discussion
RobShepherd
New Contributor
New ContributorAVALON IP LIBRARY
Hello, I am investigating the AVALON Bus Protocol as a standard to be used in a RISC-V SoC design.
I understand AVALON to be an OPEN standard but wish to understand what AVALON IP/Macros/RTL are a...
I don't know if this helps, but here are the Avalon specification and the Embedded Peripherals User Guide, which documents much of the IP included in Platform Designer in the Quartus Prime software for working with Avalon interfaces:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
The Generate HDL applies to all design in Platform Designer.
